This invention relates to a semiconductor memory devices and more particularly to an improved negative-voltage charge pump for integrated circuits, including electrically-erasable, electrically-programmable, read-only-memories (EEPROMs).
An EEPROM memory cell typically comprises a floating-gate field-effect transistor. The floating-gate of a programmed memory cell is charged with electrons, and the electrons in turn render the source-drain path under the charged floating gate nonconductive when a predetermined voltage is applied to the control gate. The nonconductive state is read by a sense amplifier as a "zero" bit. The floating-gate of a nonprogrammed cell is neutrally charged (or slightly positively or negatively charged) such that the source-drain path under the non-programmed floating gate is conductive when the predetermined voltage is applied to the control gate. The conductive state is read by a sense amplifier as a "one" bit.
Each column and row of an EEPROM array may contain thousands of floating-gate memory cells. The sources of each cell in a column are connected to a source-column line and the source-column line for a selected cell may be connected to reference potential or ground during reading of the selected cell by a sense amplifier The drains of each cell in a column are connected to a separate bitline (drain-column line) and the drain-column line for a selected cell is connected to the input of the sense amplifier during reading of the selected cell. The control gates of each cell in a row are connected to a row line, and the row line for a selected cell is connected to the predetermined select voltage during reading of the selected cell.
Circuits for generating negative voltage pulses by means of a charge-pump circuit are well-known and are used in commercially available flash EEPROMs, such as part number T29F256 manufactured and sold by Texas Instruments Incorporated. The negative-voltage charge-pump circuits used in that EEPROM are open-loop configurations in which the shape of the negative output voltage pulses is not controlled, either during the initial slope or during the final steady-state value.
A problem resulting from the open-loop circuit configurations has been that the output voltage wave-form varies considerably with the load connected to the output of the charge-pump. The output voltage is, for example, affected by phenomena including body effect and breakdown of dielectric material, both of which vary according to the particular process used to fabricate each batch of integrated circuits. In the case of nonvolatile memories having both chip-erase and block-erase capability, the load varies greatly depending upon which erase option is used. Therefore, there is a need for a circuit to provide closed-loop control of the initial slope and the final steady-state value of negative voltage pulses generated by a charge-pump circuit.